Process engineering to reduce self-aligned contact failure by reducing process-driven thermal stress on tungsten-dual poly gate stacks in sub-60 nm DRAM devices

摘要

We investigated the mechanism of stress-induced self-aligned contact (SAC) failure in sub-60 nm W-dual poly metal gate processes used in DRAM devices. We found that during the NH_3 pre-purge step of gate capping nitride deposition, the amorphous WN_x barrier and the side of the gate-etched W electrode transformed into crystallized W_2N, which experienced in-plane tensile stress to relieve the high compres-sive stress of the inner gate W. Asymmetrical relief of the W stress could create torque and result in gate leaning, which is the main reason for SAC failure during reliability testing. We showed that by reducing the NH_3 pre-purge time, we were able to dramatically reduce the incidence of gate leaning, which should yield devices with good reliability characteristics.