首页> 外国专利> STRESS-REDUCED POLYMETAL GATE ELECTRODE CAPABLE OF REDUCING MECHANICAL STRESS GENERATED FROM GATE STACK IN POST THERMAL PROCESS AND FABRICATING METHOD THEREOF

STRESS-REDUCED POLYMETAL GATE ELECTRODE CAPABLE OF REDUCING MECHANICAL STRESS GENERATED FROM GATE STACK IN POST THERMAL PROCESS AND FABRICATING METHOD THEREOF

机译:能够减小后热处理过程中门架产生的机械应力的应力减小的多金属栅电极及其制造方法

摘要

PURPOSE: A stress-reduced polymetal gate electrode and a fabricating method thereof are provided to improve a refresh characteristic and reliability by implanting ions into a low resistant metal to adjust a thermal expansion coefficient thereof. CONSTITUTION: A gate insulating layer(302) is formed on a semiconductor substrate(301). A gate stack(300) is formed on the gate insulating layer. The gate stack includes a polysilicon layer(303) as a bottom layer, a hardmask insulating layer(307) as a top layer, and a metal layer(305) formed therebetween. The metal layer has a minimum thermal expansion coefficient difference in comparison with the hardmask insulating layer and the polysilicon layer. An ion implantation buffer layer(306) is formed on the metal layer to perform a buffering function in an impurity implantation process.
机译:目的:提供一种减少应力的多金属栅电极及其制造方法,以通过将离子注入到低电阻金属中以调节其热膨胀系数来改善刷新特性和可靠性。组成:栅极绝缘层(302)形成在半导体衬底(301)上。在栅绝缘层上形成栅叠层(300)。栅极堆叠包括作为底层的多晶硅层(303),作为顶层的硬掩模绝缘层(307)以及在其之间形成的金属层(305)。与硬掩模绝缘层和多晶硅层相比,金属层具有最小的热膨胀系数差。离子注入缓冲层(306)形成在金属层上,以在杂质注入工艺中执行缓冲功能。

著录项

  • 公开/公告号KR20050009466A

    专利类型

  • 公开/公告日2005-01-25

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030048788

  • 发明设计人 CHO HEUNG JAE;LIM KWAN YONG;

    申请日2003-07-16

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:56

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号