首页> 外国专利> POLYMETAL GATE ELECTRODE HAVING STRESS BUFFER LAYER INSERTED FOR REDUCING FILM STRESS OF GATE STACK AND FABRICATING METHOD THEREOF

POLYMETAL GATE ELECTRODE HAVING STRESS BUFFER LAYER INSERTED FOR REDUCING FILM STRESS OF GATE STACK AND FABRICATING METHOD THEREOF

机译:具有应力缓冲层的聚金属栅电极,用于降低栅膜成膜应力及其制备方法

摘要

PURPOSE: A polymetal gate electrode having a stress buffer layer and a fabricating method thereof are provided to reduce film stress generated from a hardmask and stress generated from a post thermal process by inserting the stress buffer layer into an intermediate part of a polysilicon layer. CONSTITUTION: A gate insulating layer(302) is formed on a semiconductor substrate(301). A gate stack(300) is formed on the gate insulating layer. The gate stack includes a polysilicon layer(303,305) as a bottom layer, a hardmask insulating layer(308) as a top layer, and a metal layer(307) formed therebetween. A stress buffer layer(304) is inserted into an intermediate part of the polysilicon layer.
机译:目的:提供一种具有应力缓冲层的多金属栅电极及其制造方法,以通过将应力缓冲层插入多晶硅层的中间部分来减少由硬掩模产生的膜应力和由后热处理产生的应力。组成:栅极绝缘层(302)形成在半导体衬底(301)上。在栅绝缘层上形成栅叠层(300)。栅极堆叠包括作为底层的多晶硅层(303,305),作为顶层的硬掩模绝缘层(308)以及在其之间形成的金属层(307)。将应力缓冲层(304)插入到多晶硅层的中间部分中。

著录项

  • 公开/公告号KR20050009405A

    专利类型

  • 公开/公告日2005-01-25

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030048707

  • 发明设计人 CHO HEUNG JAE;LIM KWAN YONG;

    申请日2003-07-16

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:57

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