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Current Contour Based Design Methodology for IMN Design of Doherty Power Amplifiers

机译:基于电流轮廓的Doherty功率放大器IN设计方法

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摘要

Carrier aggregation (CA) is used in modern communication schemes to increase com- munication bandwidth (BW) and reduce redundant equipment. This combined with the already high peak to average power ratio (PAPR) signals in use for complex modulation schemes results in stringent linearity requirements and degradation in the average drain efficiency (DE) in basic power amplifier (PA) topologies. This has led to research interests in highly efficient broadband PAs capable of addressing the bandwidth and multi-standard requirements. Several techniques have been developed to enhance the efficiency of PAs when driven by a modulated signal with high PAPR, but amongst them the Doherty power amplifier (DPA) has garnered considerable attention in research and commercial adoption.In this work the importance of the current profiles at the drain of the main and peaking amplifier in the DPA is examined. By looking at the effect of the nonlinear capacitance at the input of the transistor, it is seen that choice of impedance presented at the fundamental and second harmonic have a drastic effect on the performance of the overall PA. To combat these issues, the constant current circle is introduced to aid in the design of the input matching network (IMN) of the main and peaking. By using the current contours the fundamental drain current can be carefully dictated by presenting the correct impedance at the gate of the transistor versus frequency and input drive. Using the current contours in conjunction with the design methodology outlined allows for the simple design of DPA IMN to extract the most performance out of the output combining node (OCN).To validate the introduced material a 12-W 3.0-5.0GHz DPA was constructed using GaN HEMT transistors. The simulation results showed that the current profiles remained within range when using an iterative design approach along with current contours. Measurement results showed that the PA was able to achieve a gain of 8dB within the designed band. As well the efficiency at both peak and BO was greater than 37% across the band. To show the performance of the PA under modulated signal, the PA was tested with a 80MHz intra- band non-contguous signal at 3.3GHz. Before DPD the reported ACLR was 37dBc/Hz. Applying a DPD engine, the ACLR was brought down to 48dBc/Hz, or the noise floor of the equipment.
机译:载波聚合(CA)用于现代通信方案中,以增加通信带宽(BW)并减少冗余设备。这与用于复杂调制方案的已经很高的峰均功率比(PAPR)信号相结合,导致严格的线性要求以及基本功率放大器(PA)拓扑中的平均漏极效率(DE)下降。这引起了对能够满足带宽和多标准要求的高效宽带PA的研究兴趣。已经开发了几种技术来提高PAPA的效率,当它们被具有高PAPR的调制信号驱动时,但其中的Doherty功率放大器(DPA)在研究和商业应用中已经引起了相当大的关注。检查DPA中主放大器和峰值放大器的漏极处。通过查看晶体管输入端的非线性电容的影响,可以看出,选择在基波和二次谐波处呈现的阻抗会对整个PA的性能产生巨大影响。为了解决这些问题,引入了恒定电流圆以帮助设计主电源和峰值电源的输入匹配网络(IMN)。通过使用电流轮廓,可以通过在晶体管的栅极呈现正确的阻抗与频率和输入驱动的关系来仔细地决定基本漏极电流。将当前轮廓与概述的设计方法结合使用,可使DPA IMN的简单设计从输出合并节点(OCN)中提取出最大的性能。为验证引入的材料,构建了12-W 3.0-5.0GHz DPA使用GaN HEMT晶体管。仿真结果表明,当使用迭代设计方法以及电流轮廓时,电流轮廓保持在范围内。测量结果表明,PA在设计频段内能够实现8dB的增益。同样,整个频段的峰值和BO效率均大于37%。为了显示功率放大器在调制信号下的性能,用3.3MHz的80MHz带内非连续信号测试了功率放大器。在DPD之前,报告的ACLR为37dBc / Hz。使用DPD引擎,ACLR降至48dBc / Hz,即设备的本底噪声。

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  • 作者

    Patel Kasyap;

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  • 年度 2015
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  • 原文格式 PDF
  • 正文语种 en
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