Progression of technology nodes in integrated circuit design is only possible if there are sustainable, cost-efficient processes by which these designs can be implemented. As future technologies are increasing device density, shrinking device dimensions, and employing novel structures, semiconductor processing must also advance to effectively and eciently process these devices. Arguably one of the most critical, inefficient, poorly understood and costly processes is planarization. Thus, this thesis focuses on two types of planarization processes. Models of efficient and environmentally benign electrochemical-mechanical copper planarization (eCMP) are developed, with a focus on electrochemical mechanisms and wafer-scale uniformity. Specifically, previous models for eCMP are enhanced to consider the full electrochemical system driving planarization in eCMP. We explore the notion of electrochemical reactions at both the cathode and anode, in addition to lateral current flow in a time-averaged calculation. More ecient and accurate models for planarization of shallow-trench isolation (STI) structures are proposed, with a focus on die-scale and feature-scale uniformity. This thesis captures the fundamental weakness of CMP, pattern dependencies, and uses deposition prole effects as well as the pattern-density to more accurately model and physically represent STI structures during CMP. We model, for the first time, the evolution of pattern density as a function of time and step-height, and use layout biasing to account for deposition prole evolution for the accurate prediction of die and feature-scale CMP.
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