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Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off

机译:用于有效利用sDRam的存储器架构:计算/存储器访问权衡的案例研究

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摘要

This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance requirement of this application is a frame rate of 25 frames per second when rendering 3D models with 2 million triangles, i.e. 50 million triangles per second, sustained (not peak). At present, a software implementation is capable of 3-4 frames per second for a 1 million triangle model. By using direct evaluation of certain interpolation parameters instead of forward differencing, writing back parameters to SDRAM is avoided. In software, forward differencing is usually better, but in this hardware implementation, the trade-off has made it possible to develop a very regular memory architecture with a buffering system, which can reach 95% bandwidth utilization using off-the-shelf SDRAM, This is achieved by changing the algorithm to use a memory access strategy with write-only and read-only phases, and a buffering system, which uses round-robin bank write-access combined with burst read-access.
机译:本文讨论了在3D图形图块渲染器中用于可视化医疗扫描仪数据的计算与内存访问之间的权衡。此应用程序对性能的要求是,在渲染具有200万个三角形(即每秒5000万个三角形)的3D模型(持续(不是峰值))时,其帧速率为每秒25帧。目前,对于一百万个三角模型,软件实现能够每秒3-4帧。通过使用某些插值参数的直接评估而不是前向差分,可以避免将参数写回SDRAM。在软件中,前向差异通常会更好,但是在这种硬件实现中,折衷使得使用缓冲系统开发非常规则的内存体系结构成为可能,使用现成的SDRAM可以达到95%的带宽利用率,这可以通过以下方法实现:将算法更改为使用具有只写和只读阶段的内存访问策略,以及一种将循环银行写访问与突发读访问结合使用的缓冲系统。

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