Central memory for access, via a multi-port memory architecture, by a number of processors has a design that incorporates a RAM machine to control memory access in a more efficient manner

摘要

Multi-port memory architecture has sequential logic control, in the form of a state automat or virtual RAM machine, that continually sequentially accesses a number of port registers, and continually exchanges addresses and data with the central memory unit. The system has variable numbers of ports, the size of which can also be scaled.