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A Very Large Scale Integrated (VLSI) circuit chip layout for a low resolution accumulator chip

机译：用于低分辨率累加器芯片的超大规模集成（VLsI）电路芯片布局

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作者
Shyu, H. C.; Reed, I. S.;
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年度 1989
页码 1-10
总页数 10
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
ARCHITECTURE (COMPUTERS); CHIPS (ELECTRONICS); CMOS; LAYOUTS; VERY LARGE SCALE INTEGRATION; ACCUMULATORS; LOGIC PROGRAMMING; MAGNETIC TAPES;

机译：建筑（计算机）;芯片（电子）; CmOs; LaYOUTs;非常大规模的集成;累加器;逻辑程序设计;磁带;

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2. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement [J] . Education, IEEE Transactions on . 2010,第2期

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3. FLOW-THROUGH CELL BASED ON AN ARRAY OF GOLD MICROELECTRODES OBTAINED FROM MODIFIED INTEGRATED CIRCUIT CHIPS [J] . Augelli MA., Pedrotti JJ., Gutz IGR., The Analyst: The Analytical Journal of the Royal Society of Chemistry: A Monthly International Publication Dealing with All Branches of Analytical Chemistry . 1997,第8期

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4. On the reliability and failure analysis of Very large Scale Integrated Circuits (VLSI Chips) [C] . S. Jahanian, K. Chatterjee Twentieth International Vlsi Multilevel Interconnection Conference (VMIC); Sep 23-25, 2003; Marina del Rey, California . 2003

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5. Low loading capacitance on-chip electrostatic discharges (ESD) protection circuits for gallium arsenide heterojunction bipolar transistor (HBT) radio frequency integrated circuits (RFIC). [D] . Ma, Yintat. 2004

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7. The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI [O] . Buehler Martin G., Linholm Loren W. 1981

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A Very Large Scale Integrated (VLSI) circuit chip layout for a low resolution accumulator chip

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