INTEGRATED DYNAMIC POWER DISSIPATION CONTROL SYSTEM FOR VERY LARGE SCALE INTEGRATED (VLSI) CHIPS

摘要

An integrated circuit arrangement for providing erase voltages to a flash EEPROM -memory array including one charge pump for generating a first high voltage withsubstantial current which may be used for application to the source terminals of flashEEPROM memory cells during erase and to the gate terminals of flash EEPROM memorycells during programming, and another charge pump for generating a second lowervoltage which may be used for application to the drain terminals of flash EEPROMmemory cells during programming.