Surface morphology evolution in silicon during ion beam processing

摘要

The Semiconductor Industry Association (SIA) projects that the semiconductor211u001echips used in personal computers and scientific workstations will reach five 211u001etimes the speed and ten times the memory capacity of the current pentium-class 211u001eprocessor by the year 2007. However, 1 GHz on-chip clock speeds and 64 Gbits/Chip 211u001eDRAM technology will not come easy and without a price. Such technologies will 211u001erequire scaling the minimum feature size of CMOS devices (the transistors in the 211u001esilicon chip) down to' below 1OOnm from the current 180 to 250 nm. This 211u001erequirement has profound implications for device manufacturing. Existing 211u001eprocessing techniques must increasingly be understood quantitatively and modeled 211u001ewith unprecedented precision. Indeed, revolutionary advances in the development 211u001eof physics-based process simulation tools will be required to achieve the goals 211u001efor cost efficient manufacturing, and to satisfy the needs of the defense 211u001eindustrial base. These advances will necessitate a fundamental improvement in our 211u001ebasic understanding of microstructure evolution during processing.