Dynamically Reconfigurable FPGA-Based Multiprocessing and Fault Tolerance

摘要

Processor replication is a straight-forward yet general method for contendingwith a range of failure modes in computing systems. Hardware-intensive solutions lower utilization by dedicating resources solely to fault tolerance. Alternately, software-intensive solutions, although flexible, require coping with slower speeds. Our objective in this research is to eliminate these problems and limitations by adding a multiprocessing capability so that the redundant hardware is used selectively. The architecture we propose is flexible in that processors do not have to be tightly synchronized, and it permits unconstrained combinations of fault-tolerant and multiprocessing applications to execute concurrently for efficient processor utilization. We capitalize on dynamically reconfigurable Field-Programmable Gate Array (FPGA) technology, which permits changing portions of its logic without disturbing the rest of the array. We demonstrate our tools and techniques for reconfiguring the FPGA, even while it operates, to create a virtual FPGA that is much larger than the physical FPGA. We have analyzed the proposed architecture and evaluated it with respect to performance, cost, scalability, reliability, and configurability. Based on all of these criteria, we have shown that our approach is superior to comparable designs.