Performance evaluation of a dynamically reconfigurable multiprocessing and fault-tolerant computing architecture

摘要

Appropriate architectures need to be developed for reconfigurable computing. A highly configurable digital system adapts to various computational tasks through reuse of its available hardware for maximum performance with minimum overhead. These systems can exploti reprogrammable field-programmable gate arrays (FPGAs) by continually reconfiguring the existing hardware, even while it operates, and thuse reduce the amount of hard-ware dedicated to system functions. In this paper, the application of these dynamically reconfigurable FPGAs is flexible fault tolerance and multiprocessing. The architecture, referred to as Dynamic Reconfigurability Assisting Fault Tolerance (DRAFT), is modeled and simulated using VHDL.