SiGe HBT BiCMOS for 2-160 Gb/s Next Generation Internet (NGI)

摘要

This Final Report describes the research related to high speed serial communication circuits implemented in SiGe HBT technology at Rensselaer Polytechnic Institute. Serializer/ Deserializer (SERDES) circuits are crucial in keeping pace with the rapidly advancing needs for high-speed data transmission in both short distance and long distance scenarios. Research was undertaken to make better use of existing long-haul infrastructure such as fiber optic networks, as well as for improving communication over much smaller scales such as those distances found on a typical PCB. Designs pushing the fundamental limits of the available manufacturing processes provide a fertile ground for developing innovative circuits in both the analog and digital realms. Work rapidly changes focus to the circuitry responsible for the most recently encountered bottleneck, be it in amplification, digital sampling, oscillators, or elsewhere. To date we have created two complete prototype designs, which were fabricated. A third design would capture 80% of the device fT as a bit rate. For IBM 5HP with an fT of 50 GHz this would be 40 Gb/s, but for a 210 GHz ft in IBM 8HP this would become 160 Gb/s. The challenge is to achieve unprecedented symmetry in the SERDES circuit and layout, as well as development of extremely low jitter VCOfs. Figure 7.15 at the end of this report shows just how good the result may be after all the circuit work is completed.