Exploration of Digital Circuits and Transistor-Level Testing in the DARPA TRUST Program.

摘要

The need to verify correct circuit operation has grown in recent years due to adversaries ability to compromise DoD systems. The DARPA program addressed this issue and implemented the DARPA TRUST program to verify untrusted circuits using software. The DARPA TRUST program was initiated in 2006 and due to this the limitations and potential errors in the program have not yet been fully explored. This research identifies the potential errors in the program by conducting transistor-level testing on circuits. The DARPA TRUST program currently operates at the gate-level and conducting various experiments at the transistor- level brought to light potential problems with current DARPA TRUST testing. The way that transistor-level verification is conducted is through netlist matching. A schematic of a circuit is created and the netlist is extracted, after that a metal layout of a circuit is created and the netlist is extracted. Once the two netlists are extracted, a matching program is used and the result determines if the verification process is successful. Parasitic capacitance was extracted in the metal layout version of a circuit and netlists were compared with the schematic version. Results show that parasitic capacitance is overlooked in the DARPA TRUST program even though this could potentially cause a fabricated device to fail. Transmission lines were simulated by creating metal wiring between two inverters. These metal lines mimic the operation of a transmission line. These transmission lines were experimented on and it was determined that the DARPA TRUST program does not effectively check for potential errors in transmission line fabrication. The results of this research brought to light the vulnerabilities in the DARPA TRUST program and addressed the need for the program to conduct transistor-level testing.