Calculation of Carriers in Depletion Region of Semiconductors with Capacitance-Voltage Measurements

摘要

Profiles obtained by the capacitance-voltage (C-V) method cannot give carrier distributions information right from the semiconductor surface. Since the prediction of ultimate device performance depends strongly upon an accurate knowledge of the entire carrier depth profile, it is very important to know this profile for the entire crystal including the surface depletion layer. A method was developed for obtaining the measured C-V data. This method was successfully applied to simulated C-V data created from various known linear, parabolic, and LSS Gaussian distributions, and then finally was demonstrated through experimentally measured C-V profiles obtained from Si-implanted GaAs. In this method, barrier potential was assumed to be 0.8 eV for n-type Si-implanted GaAs. Theses. (RH)