Vertical NPN Bipolar Junction Transistors Fabricated in Silicon-on-Sapphire

摘要

Previous attempts at fabricating vertical bipolar junction transistors (BJTs) onSilicon-on-Sapphire (SOS) have produced transistors with low Early voltages, high leakage currents and low current gain. These problems were attributed high density of microtwin and stacking fault defects at the surface of the silicon which caused enhanced diffusion of the emitter dopant across the base to the collector resulting in emitter-collector diffusion pipes. By utilizing the Double Solid Phase Epitaxy (DSPE) process and limiting the furnace anneals for the base, emitter and collector dopants the effect of emitter-collector shorts on device performance can be reduced. Vertical NPN bipolar junction transistors were fabricated on DSPE improved SOS using conventional furnace anneals. Transistors with an effective emitter area of 40 square micrometers were measured for current gain beta(DC) and Early voltage (VA). Functional devices with beta(DC) values of up to 70, VA values of 40 volts and fT values of 2.4 Gigahertz were recorded. (Author)