Reliability of Small Geometry VLSI Devices for Microelectronics

摘要

This proposal is a continuation of a project which began in August 1986. The goalof the project, in a broad sense, is to perform exploratory research into the physics of carriers in silicon inversion layers with a focus on the issues which affect the reliability of small geometry VLSI devices. This project permits us to study the physical electronics of silicon surfaces and the overlying insulators. In the proposed project we stress the application of this research to the area of Wafer Scale Integration where reliability and fault tolerance are key issues for the SDI program. The extensive signal processing and data storage required to implement high-resolution, sensor-based systems demands that consideration be given to the area of system and component reliability. At the component level the issues revolve around the reliability of the scaled MOS Transistor with nanometric feature sizes. One important area is the susceptibility of the gate insulator to (1) hot electron trapping, (2) premature dielectric breakdown, and (3) space radiation environment considerations which can limit the MTTF of the SDIO mission. A second issue at the component level is the SDI need for low-power, high-density, nonvolatile data storage with nondestructive readout (NDRO), radiation tolerance and immunity to single event upsets (SEU's).