Phonon-and surface-roughness-limited mobility of gate-all-around 3C-SiC and Si nanowire FETs

摘要

We present numerical simulations of gate-all-around (GAA) 3C-SiC and Si nanowire (NW) field effect transistors (FETs) using a full quantum self-consistent Poisson_Schr_dinger algorithm within the non-equilibrium Green's function (NEGF) formalism. A direct comparison between Si and 3C-SiC device performances sheds some light on the different transport properties of the two materials. Effective mobility extraction has been performed in a linear transport regime and both phonon-(PH) and surface-roughness-(SR) limited mobility values were computed. 3C-SiC FETs present stronger acoustic phonon scattering, due to a larger deformation potential, resulting in lower phonon-limited mobility values. Although Si NW devices reveal a slightly better electrostatic control compared to 3C-SiC ones, SR-limited mobility shows a slower degradation with increasing charge density for 3C-SiC devices. This implies that the difference between Si and 3C-SiC device mobility is reduced at large gate voltages. 3C-SiC nanowires, besides their advantages compared to silicon ones, present electrical transport properties that are comparable to the Si case.