Chip packaging 2.0 - User-definable chip pinout packaging for optimized PCB design

摘要

System designers have an ongoing need to optimize board-level designs. The cost to spin new chips from scratch is prohibitive in today's business environment. Legacy chips are routinely thrown 'over the wall' to board designers, often years after the chips were designed. In the current world, legacy chipmakers have limited interest to talk with board designers. Board designers are constrained from developing fully optimal boards in the current so-called 'Chip Packaging 1.0' environment, and there is a clear need to change. In the proposed new 'Chip Packaging 2.0' environment, board designers start with off-the-shelf legacy die (wafer) and use suitable EDA software to re-map the chip's pinout (without altering the performance of the silicon) while simultaneously optimizing the board design. The EDA software would create a bonding schedule for delivery via the internet or by conventional means to wirebonding machines for assembly. This paper poses the question what if board designers were empowered to re-map legacy chip package pinouts, in order to design optimum boards in a Chip Packaging 2.0 world?