Structural Optimization of Tunnel FET on SOI (Silicon-On-Insulator) substrate for Sub-0.5V Application

摘要

This paper presents simulation works on the structural optimization of tunnel FET (TFET) on silicon-on-insulator (SOI) substrate for sub-0.5V application. Optimization is done with several structural parameters including SOI film thickness, gate structure of front and back gate, gate oxide thickness (front and back), and overlap width of gate and source regions. It has been observed that from the performance point of view, the key design factors are SOI film thickness, overlap of gate and source regions and double gate structure. The best performance of TFET has been achieved with structural parameters such as SOI film comparable to gate length, zero overlap of gate and source regions and double gate structure with same oxide thickness at top and bottom gate.