Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs

摘要

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient solution for power savings. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this article, we propose a load-balanced clock tree synthesizer with Adjustable Delay Buffer (ADB) insertion for clock skew reduction in MDSV designs. The clock tree synthesizer adopts the Minimum Spanning Tree (MST) metric to estimate the interconnect capacitance and execute the graph-theoretic clustering. The power-mode-guided optimization is also embedded into the clock tree synthesizer for improving additional area overhead in the step of ADB insertion. After constructing the initial buffered clock tree, we insert the ADBs with delay value assignments to reduce clock skew in MDSV designs. The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm of ADB insertion, experimental results show maximum 42.40% area overhead improvement. With the power-mode-guided optimization, the maximum improvement of area overhead can increase to 47.87%.