Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures

摘要

We examined the characteristics of the DRAM cell transistor's retention time by extracting the electric field peak values and their positions using a new simulation method with traps. In order to enhance the retention time, it is essential to reduce the electric field at the storage node junction, which should be performed by decrease the channel doping level without any change in the threshold voltage. We compared the planar gate structure with the non-planar, and the symmetric doping profiles with the asymmetric ones.