Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage

摘要

A vertical-gate Si/SiGe double heterojunction bipolar transistor (VerDHBT)-based capacitorless 1T DRAM cell is proposed for improved storage performance with a fabrication feasibility through a selective epitaxy. It is verified through a TCAD device simulation for dc and transient characteristics of the proposed VerDHBT-based 1T DRAM. The off-state leakage current was significantly reduced, while the on-current was considerably increased with $S_{rm IF}/B_{rm mid}/D_{rm IF} = hbox{SiGe/SiGe/Si}$ as the interfacial source/middle body/interfacial drain. A large hysteresis window for the “read 1” from the “read 0” and a long retention time at low latch voltage could be also obtained.