Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time

摘要

A capacitorless dynamic random access memory (DRAM) cell is proposed for low voltage operation with device scaling-down. The proposed DRAM cell features low body doping concentration and recessed gate. Low doping body is introduced to use punch-through as a program mechanism. Punch-through occurs easily in the case of low doping body concentration. Therefore low doping body allows high speed operation in spite of low operation voltage. However low doping body leads to severe drain induced barrier lowering (DIBL). DIBL reduces data retention time. Recessed gate structure can suppress DIBL and increase data retention time. Finally, The proposed capacitorless DRAM cell has long data retention time and operates with low operating voltage.