Semiconductor memory device with complementary floating body transistor capacitorless memory cells e.g. dynamic random access memory (DRAM) has voltage sense amplifier provided to amplify voltage differential between complementary bit lines

摘要

The device has complementary first and second bit lines (BL,BLB), and a unit memory cell (TMC) that includes complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary bit lines. A voltage sense amplifier (S/A) is connected between the complementary bit lines to amplify the voltage differential between the complementary bit lines. A capacitive coupling is arranged between the bit lines to cause a negative basis to write or restore a threshold voltage of one of the floating body transistor capacitorless memory cells. Independent claims are included for the following: (1) Writing or restoring a threshold voltage of a floating body transistor capacitorless memory cell device; and (2) Operation method of the semiconductor memory device.