In this paper, the result of varying the supply voltage on the operation, speed and current supply of four voltage sense amplifier circuits for 1-Transistor DRAM memories is investigated. Utilizing the half-Vdd pre-charge, the sense amplifiers are designed to achieve the highest possible gain and noise margin, and are implemented in a 90nm CMOS technology. For a supply of 1.2V, the Current Mirror Sense Amplifier with Cross Latch Stage at the Output achieved the highest gain of −31.4, while the Full Latch Sense Amplifier consumes the least current at 92.2uA and produces the highest noise margin among the four topologies. Simulations also verify the decrease on the speed of the sense amplifiers with the lowering of the voltage supply as manifested on the slew rate, but with an expected improvement on the current consumption.
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