Optimization of lateral diffusion of source and drain for bus-100-nm channel silicon-on-insulator MOSFETs

摘要

This paper investigates how the lateral diffusion extent (L{sub}(1d)) of source and drain regions influences device characteristics of short-channel SOI MOSFETs. Since L{sub}(1d)-scaling involves a trade-off between the maximal carrier velocity (v{sub}(max)) and the threshold voltage (V{sub}(th)) the optimization of L{sub}(1d) is indispensable However, even after Lid is optimized in some way, it is found that the net performance advancement offered by device-scaling is quite limited. It follows that in designing sub-100 nm SOI devices, high-k material and new doping materials, such as Sb or In should be introduced.