Closed expressions for power dissipations of CMOS logic gates and their application to CMOS circuitries

摘要

We have developed simple and closed expressions for both a short-circuit power dissipation (p{sub}s) and a charge-discharge power dissipation (p{sub}D) of a single CMOS logic gate. p{sub}s is expressed by the number (m) of logic gates parallel to a given logic gate and the number (n) of fan-outs of the same gate. p{sub}s and p{sub}D expressions for various logic gates including NOT, NAND, NOR, AND-NOR and OR-NAND have been obtained so that the power dissipation of even large circuitries can be easily estimated without using CAD tools, since both m and n are known factors. We applied these expressions to an 8-bit ripple carry adder and an 8-bit square-root, divider circuit. The calculated power dissipations with these expressions were almost the same as these with SPICE.