Accurate power estimation of CMOS digital circuits and its application to low-power digital logic synthesis.

摘要

As mobile and portable information systems are becoming more popular, there is a need for the development of low-power and high-speed design technology to handle excess heat dissipation, reliability concerns, and battery life. On the other hand, deep submicron processes are pushing higher levels of integration, which increases power density and the number of transistors in VLSI circuits. As a result, it has become important to consider power dissipation and reliability issues during the design phase. In order to design circuits for low power and high reliability, accurate estimation of power dissipation is required. In CMOS digital circuits, the majority of the power dissipation is due to charging and discharging of load capacitances of logic gates. Such charging and discharging depends on input signal patterns. To estimate average power dissipation, trying all possible combinations of primary inputs is computationally too expensive. In this thesis, we have developed techniques to accurately estimate power dissipation in CMOS combinational and sequential circuits using probabilistic and statistical approaches. We model the primary inputs as stochastic processes such that each input signal is characterized by signal probability and activity. These approaches take into account temporal and spatial correlations of signals of circuit nodes, power dissipation due to charging and discharging of internal nodes of logic gates, and uncertainty of gate delays. The estimation techniques have been implemented in the C programing language. Results of the estimation techniques show that the errors are on an average within 5% of the results obtained by long run simulation. The probabilistic technique has been applied to combinational logic synthesis to optimize for power and area. Results show that the power consumption is reduced by 10% (on an average) with minimal increase in area.