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Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation
Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation
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机译:具有低有源泄漏功耗的多电源电压拉链CMOS逻辑系列
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摘要
An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.
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