ESD performance of LDMOS with source-bulk layout structure optimization

摘要

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger I_(t2) than a conventional one, and its V_(t1) is reduced from 55.53 to 50.69 V.