Layout geometry impact on nLDMOS devices for high-voltage ESD protection

摘要

N-channel, lateral, double-diffused MOS (NLDMOS) devices with finger-type, square-type, and octagon-type layout styles are investigated and fabricated in a 0.5-μm 18 V CMOS-DMOS (CDMOS) process. The square-type nLDMOS achieves the highest ESD failure current of 4.7 A and is also the device occupying the smallest chip area among the three layout styles. In view of the area efficiency, the square-type structure provides more than 30 and 25% higher current handling capability per area than the traditional finger-type and octagonal-type structures, respectively. Because of its better area efficiency, the square-type structure is a promising layout for nLDMOS in high-voltage ESD protection applications.