Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance

摘要

Coupling capacitance between adjacent wires in the on-chip interconnects significantly increases the average transition energy dissipation, and the maximum delay. This paper proposes an encoding scheme to, further, reduce the coupling energy dissipation, delay and energy delay product. Specifically, for 65 nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, delay by 24% and energy delay product by 55%, without any additional area penalty, while requiring a less complex circuit overhead when compared with the transition pattern coding (TPC) scheme. Further, we apply this scheme, to a 16-bit bus with due consideration given to the energy loss at the interfaces.