A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder

摘要

This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by a continuous-time linear equalizer (CTLE) then sampled into four branches of decoders by 1/4-rate clocks. The proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) decoder performs gain adaptation and amplitude rectification simultaneously for decoding the least significant bit (LSB). The linear sense amplifier in the AVGR is modified from a latch to achieve a high gain and low power. Compared with the full-rate receiver adopting a decoder consisting of three comparators, this design achieves a better power efficiency by employing a 1/4-rate topology and merging a variable-gain function into the decoder. Experimental results demonstrate that the receiver chip can receive and decode a 24-Gb/s 190-mV(pp) PAM4 signal at a BER of 10(-11) and a bit efficiency of 1.38 pJ/bit.