Automated pin grid array package routing on multilayer ceramic substrates

摘要

In the packaging router, routing is divided into two phases: topological routing and physical routing. Topological routing determines the topology of the paths layer by layer. Instead of using minimal spacing rules, for the given electrical constraints, the algorithm uses weighted spacing rules to optimize I/O performance. Physical routing builds the detailed structures of the connections. It permits variable RLC trade-offs. The overall time complexity is linear in the number of I/O pins. A practical packaging router was implemented. The experimental results show that this routing tool significantly improved the performance and the productivity of packaging design.