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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Reliability of majority voting based VLSI fault-tolerant circuits
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Reliability of majority voting based VLSI fault-tolerant circuits

机译:基于多数表决的VLSI容错电路的可靠性

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摘要

The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model.
机译:利用故障注入仿真方法研究了补偿模块故障对基于多数投票的VLSI容错电路可靠性的影响。这种仿真方法有助于考虑复制电路模块以及多数表决电路中的多个故障,以说明以下事实:在VLSI实现中,多数表决电路由与构成电路的可靠性相同的组件构成模块。从故障注入仿真中,获得了生存能力分布,当与区域开销表达式结合使用时,可以为基于多数表决的VLSI容错电路提供更准确的可靠性模型。扩展了新模型,以方便计算具有持续故障但继续正常运行的容错电路的可靠性。对可靠性模型的分析表明,对于某些电路,使用多数表决技术获得的可靠性显着高于任何先前模型所预测的可靠性。

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