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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Reliability of majority voting based VLSI fault-tolerant circuits
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Reliability of majority voting based VLSI fault-tolerant circuits

机译:基于多数表决的VLSI容错电路的可靠性

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摘要

The effect of compensating module faults on the reliability ofnmajority voting based VLSI fault-tolerant circuits is investigated usingna fault injection simulation method. This simulation method facilitatesnconsideration of multiple faults in the replicated circuit modules asnwell as the majority voting circuits to account for the fact that, innVLSI implementations, the majority voting circuits are constructed fromncomponents of the same reliability as those used to construct thencircuit modules. From the fault injection simulation, a survivabilityndistribution is obtained which, when combined with an area overheadnexpression, leads to a more accurate reliability model for majoritynvoting based VLSI fault-tolerant circuits. The new model is extended tonfacilitate the calculation of reliability of fault-tolerant circuitsnwhich have sustained faults but continue to operate properly. Analysisnof the reliability model indicates that, for some circuits, thenreliability obtained with majority voting techniques is significantlyngreater than predicted by any previous model
机译:利用故障注入仿真方法,研究了补偿模块故障对基于多数投票的VLSI容错电路可靠性的影响。这种仿真方法有助于对复制电路模块以及多数表决电路中的多个故障进行考虑,以说明以下事实:在nVLSI实现中,多数表决电路由与用于构造随后的电路模块的组件具有相同可靠性的n个组件构成。通过故障注入仿真,获得了生存能力分布,当与区域开销压缩结合使用时,可以为基于多数表决的VLSI容错电路提供更准确的可靠性模型。扩展了新模型,方便了具有持续故障但继续正常运行的容错电路的可靠性计算。对可靠性模型的分析表明,对于某些电路,多数表决技术所获得的可靠性比以前的模型所预测的要高得多。

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