Precomputation-based sequential logic optimization for low power

摘要

We address the problem of optimizing logic-level sequentialncircuits for low power. We present a powerful sequential logicnoptimization method that is based on selectively precomputing the outputnlogic values of the circuit one clock cycle before they are required,nand using the precomputed values to reduce internal switching activitynin the succeeding clock cycle. We present two different precomputationnarchitectures which exploit this observation. The primary optimizationnstep is the synthesis of the precomputation logic, which computes thenoutput values for a subset of input conditions. If the output values cannbe precomputed, the original logic circuit can be “turnednoff” in the next clock cycle and will have substantially reducednswitching activity. The size of the precomputation logic determines thenpower dissipation reduction, area increase and delay increase relativento the original circuit. Given a logic-level sequential circuit, wenpresent an automatic method of synthesizing precomputation logic so asnto achieve maximal reductions in power dissipation. We presentnexperimental results on various sequential circuits. Up to 75%nreductions in average switching activity and power dissipation arenpossible with marginal increases in circuit area and delay