STATE ASSIGNMENT OPTIMIZATION DEVICE FOR SYNCHRONOUS SEQUENTIAL CIRCUIT, STATE ASSIGNMENT OPTIMIZATION METHOD FOR SYNCHRONOUS SEQUENTIAL CIRCUIT, LOGIC COMPOUNDING DEVICE, PROGRAM AND READABLE RECORDING MEDIUM

摘要

PPROBLEM TO BE SOLVED: To reduce a circuit area by obtaining a state assignment solution whose circuit area is the minimum from among state assignment solution candidates in the design process of a synchronous sequential circuit. PSOLUTION: This device for optimizing the state assignment of a synchronous sequential circuit is provided with a code extension means 41 for generating a state assignment solution (state assignment code extension solution) by adding parity inspection bits to a state assignment initial solution in a device for optimizing the state assignment of a synchronous sequential circuit; a code reducing means 42 for erasing one digit of a code from the state assignment code extension solution, and for generating a plurality of state assignment candidates (state assignment code reduction solutions); and a circuit area comparing means 43 for detecting the state assignment code reduction solutions for determining a circuit whose area is the minimum by comparing circuit areas with each other based on a plurality of circuit diagram information logically compounded by using each of the plurality of state assignment code reduction solutions. PCOPYRIGHT: (C)2009,JPO&INPIT