An optimization approach to the synthesis of multichiparchitectures

摘要

An optimization approach to the high level synthesis of VLSInmultichip architectures is presented in this paper. This research isnimportant for industry since it is well known that these early highnlevel decisions have the greatest impact on the final VLSInimplementation. Optimal application-specific architectures arensynthesized here to minimize latency given constraints on chip area, I/Onpin count and interchip communication delays. A mathematical integernprogramming (IP) model for simultaneously partitioning, scheduling, andnallocating hardware (functional units, I/O pins, and interchip busses)nis formulated. By exploiting the problem structure, using polyhedralntheory, the size of the search space is decreased and a new variablenselection strategy is introduced based on the branch and boundnalgorithm. Multichip optimal architectures for several examples arensynthesized in practical cpu times. Execution times are comparable tonprevious heuristic approaches, however there are significantnimprovements in optimal schedules and allocations of multichips. Thisnresearch breaks new ground by 1) simultaneously partitioning,nscheduling, and allocating in practical cpu times, 2) guaranteeingnglobally optimal architectures for multichip systems for a specificnobjective function, and 3) supporting interchip communication delay,ninterchip bus allocation, and other complex interface constraints