Critical paths in circuits with level-sensitive latches

摘要

This paper extends the classical notion of critical paths inncombinational circuits to the case of synchronous circuits that usenlevel-sensitive latches. Critical paths in such circuits arise fromnsetup, hold, and cyclic constraints on the data signals at the inputs ofneach latch and may extend through one or more latches. Two approachesnare presented for identifying these critical paths and verifying theirntiming. The first implicitly checks all paths using a relaxation-basednsolution procedure. Results of this procedure are used to calculatenslack values, which in turn identify satisfied and violated criticalnpaths. The second approach is based on a constructive algorithm whichngenerates all the critical paths in a circuit and then verifies thatntheir timing constraints are satisfied. Algorithms are evaluated andncompared using circuits from the ISCAS89 sequential benchmark suite andnthe Michigan High Performance Microprocessor Project