Planar clock routing for high performance chip and packageco-design

摘要

A new concept of chip and package co-design for the clock networknis presented in this paper. We propose a two level clock distributionnscheme which partitions the clock network into two levels. First, thenclock terminals are partitioned into a set of clusters. For eachncluster, a local on-chip clock tree is used to distribute the clocknsignal from a locally inserted buffer to terminals inside this cluster.nThe clock signal is then distributed from the main clock driver to eachnof local buffers by means of a global clock tree, which is a planar treenwith equal path lengths. With the flip chip area I/O attachment, thenplanar global clock tree can be put on a dedicated package layer. Theninterconnect on the package layer has two to four order smallernresistance than that on the chip layer. The main contribution of thisnpaper is a novel algorithm to construct a planar clock tree with equalnpath lengths-the length of the path from the clock source to eachndestination is exactly the same. In addition, the path length from thensource to destinations is minimized