A CMOS IC for Gb/s Viterbi decoding: system design and VLSIimplementation

摘要

At present, the Viterbi algorithm (VA) is widely used inncommunication systems for decoding and equalization. The achievablenspeed of conventional Viterbi decoders (VD's) is limited by the inherentnnonlinear add-compare-select (ACS) recursion. The aim of this paper isnto describe system design and VLSI implementation of a complex system ofnfabricated ASIC's for high speed Viterbi decoding using then“minimized method” (MM) parallelized VA. We particularlynemphasize the interaction between system design, architecture and VLSInimplementation as well as system partitioning issues and the resultingnrequirements for the system design flow. Our design objectives were 1)nto achieve the same decoding performance as a conventional VD using thenparallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, andn3) to realize a system for this task using a single cascadable ASIC.nWith a minimum system configuration of four identical ASIC's produced bynusing 1.0 Μ CMOS technology, the design objective of a decoding speednof 1.2 Gb/s is achieved. This means, compared to previousnimplementations of Viterbi decoders, the speed is increased by an ordernof magnitude