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A dynamically reconfigurable interconnect for array processors

机译:可动态重新配置的阵列处理器互连

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Reconfigurability of processor arrays is important due to two reasons (1) to efficiently execute different algorithms and (2) to isolate faulty processors. An array processor that is reconfigurable by the user any number of times to yield a different topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to configure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different configurations by sending a different set of bits to the configuration random access memory (RAM) in the interconnect. We present three designs reconfigurable into array, ring, mesh, or Illiac mesh topologies. The first design provides no redundancy or fault tolerance. The second design is capable of graceful degradation by bypassing faulty elements. The third design is capable of graceful degradation by rerouting. The details of the interconnect and the configuration RAM contents for typical configurations are illustrated. It is seen that reconfigurable interconnect results in a highly reconfigurable or polymorphic computer.
机译:处理器阵列的可重新配置性很重要,原因有两个:(1)有效执行不同算法的原因和(2)隔离故障处理器的原因。本文提出了一种阵列处理器,用户可以对其进行多次配置,以产生不同的拓扑或隔离故障。该系统具有主机或控制器,该主机或控制器向互连广播命令,以将自身配置为特定方式。互连使用静态RAM编程技术,并且可以通过将不同的位集发送到互连中的配置随机存取存储器(RAM)来编程为不同的配置。我们提出了三种可重新配置为阵列,环形,网格或Illiac网格拓扑的设计。第一种设计不提供冗余或容错能力。第二种设计能够通过绕过故障元件而适度降级。第三种设计能够通过重新路由而适度降级。说明了互连的详细信息和典型配置的配置RAM内容。可以看出,可重配置的互连导致了高度可重配置或多态的计算机。

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