A dynamically reconfigurable interconnect for array processors

摘要

Reconfigurability of processor arrays is important due to twonreasons (1) to efficiently execute different algorithms and (2) tonisolate faulty processors. An array processor that is reconfigurable bynthe user any number of times to yield a different topology or to isolatenfaults is envisaged in this paper. The system has a host or controllernthat broadcasts a command to the interconnect to configure itself into anparticular fashion. The interconnect uses static-RAM programmingntechnology and can be programmed to different configurations by sendingna different set of bits to the configuration random access memory (RAM)nin the interconnect. We present three designs reconfigurable into array,nring, mesh, or Illiac mesh topologies. The first design provides nonredundancy or fault tolerance. The second design is capable of gracefulndegradation by bypassing faulty elements. The third design is capable ofngraceful degradation by rerouting. The details of the interconnect andnthe configuration RAM contents for typical configurations arenillustrated. It is seen that reconfigurable interconnect results in anhighly reconfigurable or polymorphic computer