This paper presents novel hybrid carry-select modified-tree (CSMT) adder architectures for binary carry generators and adders using multiplexers only. These architectures not only require the fewest number of multiplexers, but also consume the least energy for a specified latency. These architectures are based on a carry-select configuration where each block can be a carry-select or tree or modified-tree block. The modified-tree blocks permit ripple in the carry-generation process; which leads to dramatic reduction in the number of multiplexers as well as power consumption. It is shown that, for a block length W, the carry-select block and the modified-tree block with internal ripple of (log/sub 2/ W-1) multiplexer stages require the same number of multiplexers. This is a powerful result because the longer carry-select blocks can be replaced by the modified-tree blocks without increasing the multiplexer complexity. The advantage of this approach is in reduction of power consumption since the amount of ripple in the carry-select block grows linearly with W, while that in the modified-tree block grows logarithmically with W. It is shown that for fastest adder/subtractor designs, the proposed CSMT architecture can reduce the multiplexer complexity by about 40% for word-lengths ranging from 8 to 32, when compared with known tree approaches. It is shown that, for a certain specified latency and specified number of multiplexers, a family of carry-select and CSMT adders can be designed. It is shown that, for a specified latency, the carry-select adders with larger number of blocks and smaller block lengths consume less power. Through extensive simulations, CSMT adder configurations that minimize energy consumption or power-latency product, which are approximately 5% to 10% less than those of known tree and best carry-select adders, are obtained. Finally, based on novel latency-matching and block-increment techniques introduced in this paper, a systematic design methodology for design of CSMT adders with least latency, least number of multiplexers, and least energy consumption is presented.
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机译：本文介绍了仅使用多路复用器的二进制进位生成器和加法器的新型混合进位选择修改树（CSMT）加法器体系结构。这些架构不仅需要最少数量的多路复用器，而且在指定的等待时间中消耗的能量最少。这些架构基于进位选择配置，其中每个块可以是进位选择或树或修改后的树块。修改后的树块会在进位生成过程中产生波动；从而大大减少了多路复用器的数量以及功耗。示出了，对于块长度W，（log / sub 2 / W-1）多路复用器级的具有内部纹波的进位选择块和修改树块需要相同数量的多路复用器。这是有力的结果，因为较长的进位选择块可以用修改树块替换，而不会增加多路复用器的复杂性。这种方法的优势在于降低了功耗，因为进位选择模块中的纹波量随W线性增长，而修改树模块中的纹波量随W呈对数增长。这表明，最快的加法器/减法器设计与已知的树形方法相比，对于8至32的字长，建议的CSMT体系结构可以将多路复用器的复杂度降低约40％。结果表明，对于某些特定的等待时间和特定数量的多路复用器，可以设计一系列进位选择和CSMT加法器。结果表明，对于指定的等待时间，具有更大块数和较小块长度的进位选择加法器消耗的功率更少。通过广泛的仿真，可以获得CSMT加法器配置，该配置可将能耗或电源延迟乘积降到最低，这比已知树和最佳进位选择加法器的能耗低约5％至10％。最后，基于本文介绍的新颖的等待时间匹配和块递增技术，提出了一种用于设计CSMT加法器的系统设计方法，该方法具有最小的等待时间，最少的复用器数量和最少的能耗。
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