A coding framework for low-power address and data busses

摘要

This paper presents a source-coding framework for the design ofncoding schemes to reduce transition activity. These schemes are suitednfor high-capacitance buses where the extra power dissipation due to thenencoder and decoder circuitry is offset by the power savings at the bus.nIn this framework, a data source (characterized in a probabilisticnmanner) is first passed through a decorrelating function f1.nNext, a variant of entropy coding function f2 is employed,nwhich reduces the transition activity. The framework is then employed tonderive novel encoding schemes whereby practical forms for f1nand f2 are proposed. Simulation results with an encodingnscheme for data buses indicate an average reduction in transitionnactivity of 36%. This translates into a reduction in total powerndissipation for bus capacitances greater than 14 pF/b in 1.2 Μm CMOSntechnology. For a typical value for bus capacitance of 50 pF/b, there isna 36% reduction in power dissipation and eight times more power savingsncompared to existing schemes. Simulation results with an encoding schemenfor instruction address buses indicate an average reduction inntransition activity by a factor of 1.5 times over known coding schemes