首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning
【24h】

A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning

机译:基于非均匀细粒度表划分的MPEG-2低功率可变长度解码器

获取原文
获取原文并翻译 | 示例

摘要

Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.
机译:可变长度编码是数字视频压缩系统中广泛使用的技术。先前与可变长度解码器(VLD)有关的工作主要针对高吞吐量应用,但是对便携式多媒体系统的需求增加使功率成为非常重要的因素。本文提出了一种数据驱动的可变长度解码架构,该架构利用可变长度代码的信号统计来降低功耗。该方法使用细粒度查找表(LUT)分区来减少基于码字频率的开关电容。 MPEG-2的完整VLD已经制造出来,并使用0.6- / spl mu / m CMOS技术以1.35 V的速度消耗530 / spl mu / W,视频速率为48-M离散余弦变换样本/ s。与具有单个LUT的常规并行解码方案相比,功率降低了一个数量级以上,而且性能没有降低。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号