A low power variable length decoder for MPEG-2 based on nonuniformfine-grain table partitioning

摘要

Variable length coding is a widely used technique in digital videoncompression systems. Previous work related to variable length decodersn(VLDs) was primarily aimed at high throughput applications, but thenincreased demand for portable multimedia systems has made power a verynimportant factor. In this paper, a data-driven variable length decodingnarchitecture is presented, which exploits the signal statistics ofnvariable length codes to reduce power. The approach uses fine-grainnlookup table (LUT) partitioning to reduce switched capacitance based onncodeword frequency. The complete VLD for MPEG-2 has been fabricated andnconsumes 530 ΜW at 1.35 V with a video rate of 48-M discrete cosinentransform samples/s using a 0.6-Μm CMOS technology. More than annorder of magnitude power reduction is demonstrated without performancenloss compared to a conventional parallel decoding scheme with a singlenLUT