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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Reducing power by optimizing the necessary precision/range of floating-point arithmetic
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Reducing power by optimizing the necessary precision/range of floating-point arithmetic

机译:通过优化必要的浮点运算精度/范围来降低功耗

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Low-power systems often find the power cost of floating-point (FP) hardware prohibitively expensive. This paper explores ways of reducing FP power consumption by minimizing the bitwidth representation of FP data. Analysis of several FP programs that manipulate low-resolution human sensory data shows that these programs suffer no loss of accuracy even with a significant reduction in bitwidth. Most FP programs in our benchmark suite maintain the same output even when the mantissa bitwidth is reduced by half. This FP bitwidth reduction can deliver a significant power saving through the use of a variable bitwidth FP unit. Our results show that up to 66% reduction in multiplier energy/operation can be achieved in the FP unit by this bitwidth reduction technique without sacrificing any program accuracy.
机译:低功率系统通常会发现浮点(FP)硬件的功率成本过高。本文探讨了通过最小化FP数据的位宽表示来减少FP功耗的方法。对处理低分辨率人类感觉数据的几个FP程序的分析表明,即使位宽显着减少,这些程序也不会损失准确性。即使尾数位宽减少一半,我们基准套件中的大多数FP程序仍保持相同的输出。 FP位宽的减少可通过使用可变位宽FP单元显着节省功耗。我们的结果表明,通过这种位宽缩减技术,FP单元中的乘法器能量/运算最多可降低66%,而不会牺牲任何程序精度。

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